1. Field of the Invention
This invention relates to the field of processors for data-processing systems, and in particular to a method for generating PC-relative addresses in a processor having a pipe line architecture.
2. Description of the Related Art
In a data-processing system the basic logical arithmetic computational operations are performed by the processor. The processors use a processor core operating under control of program instruction words, which when decoded serve to generate control signals to control the different elements within the processor core to perform the necessary functions to achieve the processing specified in the program instruction word. For this purpose there is provided within the processor core a number of registers and logic circuits. The processor registers are used to receive, hold, and transmit information (data and instructions) used by the processor. Several different types of registers are provided within the typical processor core. For example, an accumulator register temporarily stores data and accumulates the results of logical or arithmetic operations. A program counter stores the address of the next instruction in memory to be executed. An instruction register stores the instruction code (also known as the operation code) portion of instruction which is currently being executed by the processor, and an address register or data counter stores the operand portion of the currently executing instruction.
To enable the processor to perform all of the intended arithmetic and logical operations which are desired to be performed, the processor is provided with the capability of executing a repertory of individual instructions collectively known as an instruction set. Individual instructions are executed by the processor to perform such operations as loading information into a register, transferring information between registers or between registers and memory, comparing the contents of two registers, and so forth. Such instructions may be thought of as "macro-instructions" since the execution of one such instruction by the processor typically comprises a number of sub-operations or "micro-instructions" by the circuitry making up the instruction execution control logic portion of the processor. During the execution of a single instruction many different logic gate in the instruction execution control logic circuitry may be opened and closed in a precise sequence in order to implement the particular macro-operation called for by the instruction. The opening or closing of each gate may be individually viewed as a single micro-instruction.
Processor architectures may generally be classified as either complex instruction set (computing (CISC) architectures or reduced instruction set computing (RISC) architectures. CISC architectures specify an instruction set comprising high level, relatively complex instructions (i.e. many micro-instructions for each macro-instruction). Microcoded routines stored in an on-chip read-only memory (ROM) have been suceessfully employed to provide the micro-instruction operations corresponding to a macro-instruction. More recently, hardware decoders which separate the complex instructions into simpler operations have been adopted by certain CISC microprocessor designers. The x86 microprocessor architecture is an example of a CISC architecture.
Conversely, RISC architectures specify an instruction set comprising low level, relatively simple instructions (very few, perhaps even one, micro-instructions per macro-instruction). Typically, each instruction within the instruction set is directly implemented in hardware. Complexities associated with the CISC approach are removed, allowing for more advanced implementations to be designed. Additionally, high frequency designs may be achieved more easily since the hardware employed to execute the instructions is simpler. An exemplary RISC architecture is the MIPS RISC architecture.
A commonly employed instruction in many instruction sets is the "load" instruction, in which a data value is retrieved from a specified memory location and stored in a processor register. The complement of this instruction, in which a data value is retrieved from a processor register and stored in a specified memory location, is often known as the "store" instruction. These and other instructions cause the microprocessor to initiate a memory access.
Generally, a memory access by the processor requires the provision of a target address. Three existing addressing techniques are described in the literature. The first is absolute addressing in which the target address is usually fully specified within the literal field of an instruction. The second is register offset addressing in which the literal is taken as an offset to an address contained in a register. The third is relative addressing in which the literal is taken as an offset from the current PC (program counter) address.
Absolute addressing causes one of two problems depending upon the implementation. As it is generally used, it must allow for the embedded literal field to the same size as the target address (K bits for a 2.sup.K byte memory). This is very costly since more memory is required to store these bits, and a larger memory bandwidth is required to load the instructions along with a fully specified address. If absolute addresses are used with a literal field that is smaller than K bits, then absolute addressing cannot provide an addressing range independent of the PC.
Relative addressing reduces the size of the address field, and takes advantage of the fact that most addresses can be arranged to be within a small range around the value of the PC. For a J+1 bit field, the relative address range is usually from -2.sup.j to 2.sup.j -1. Relative addressing places additional hardware and timing requirements on the system to ensure that the offset gets added to the PC.
A technique known as pipelining is often used to enhance the speed and performance of processors. In this technique the execution of instructions is divided into stages, and the stages are overlapped so that multiple instructions may be simultaneously execued. In a pipeline structure, instructions enter at one end--are processed through the stages or pipe segments--and exit at the other end. Each of the stages of the pipeline completes a part of the instruction.
Although program execution for the most part moves through program instructions sequentially, branch instructions (herein the term "branch instructions" is taken to include unconditional branch, or "jump", instructions) provide a mechanism by which program instructions may be executed out of sequence. Hence an instruction pipeline is not necessarily working on a series of sequential instructions, and the fetch program counter register cannot necessarily be used to determine the program counter values of instructions in other stages of the pipeline.
It will be appreciated that the use of pipelining complicates the implementation of the generally desirable feature of relative addressing, since multiple instructions (each having a distinct PC) are simultaneously being executed, and the PC of the instruction being executed by the execute stage is generally unknown. It would be desirable to have an efficient implementation so that this feature may be provided without overly much additional complexity and cost.